Custom Design of Full Pipeline SHA-256 Algorithm Based on Dynamic Pulsed Latch

Abstract: In the full pipeline implementation of SHA-256 algorithm, registers occupy a significant portion of the area. To reduce the cost of registers, we introduce the simplest dynamic pulsed latch (DPL) composed of only one inverter and one transmission gate as the data register. As the DPL exhibits inverted storage characteristic, we also modify all the suboperators in the SHA-256 algorithm, including CSA, MAJ, CH, ∑0, ∑1, σ0 and σ1, enabling them to accommodate input data with different polarities. Using a customized approach, we have designed and implemented a 130-stage full pipeline circuit, incorporating two SHA-256 algorithms, based on a 14 nm FinFET technology. The entire core occupies an area of approximately 0.1 mm2, resulting in a 60% area reduction compared to the traditional full pipeline circuit based on dynamic D flip-flops. Test results indicate that under 27 °C and 0.8 V power supply conditions, the average power-delay product of the entire 130stage full pipeline SHA-256 circuit is approximately 345 mW*ns.

Keywords: Custom design, Full pipeline, Dynamic pulsed latch, SHA-256, Compressor, Expander, FinFET process

Recommended citation: Z. Zhang et al., "Custom Design of Full Pipeline SHA-256 Algorithm Based on Dynamic Pulsed Latch," in IEEE Transactions on Consumer Electronics, doi: 10.1109/TCE.2026.3659576.
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